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ADuM5401W/ADuM5402W/ADuM5403W
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component (see Figure 24).
The propagation delay to a logic low output may differ from the
propagation delay to a logic high.
Data Sheet
As a result, the ADuM5401W/ADuM5402W/ADuM5403W
devices can draw large amounts of current at low voltage for
extended periods of time.
The output voltage of the ADuM5401W/ADuM5402W/
ADuM5403W devices exhibits VISO overshoot during startup.
INPUT (V Ix )
OUTPUT (V Ox )
t PLH
t PHL
50%
50%
If this overshoot could potentially damage components attached
to V ISO , a voltage-limiting device such as a Zener diode can be
used to clamp the voltage. Typical behavior is shown in Figure 17
and Figure 18.
Figure 24. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these
two propagation delay values and is an indication of how
accurately the input signal timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM5401W/ADuM5402W/ADuM5403W component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM5401W/
ADuM5402W/ADuM5403W components operating under
the same conditions.
START-UP BEHAVIOR
The ADuM5401W/ADuM5402W/ADuM5403W do not
contain a soft start circuit. Therefore, the start-up current and
voltage behavior must be taken into account when designing
with these devices.
When power is applied to V DD1 , the input switching circuit begins
to operate and draw current when the UVLO minimum voltage
is reached. The switching circuit drives the maximum available
power to the output until it reaches the regulation voltage where
PWM control begins. The amount of current and the time
required to reach regulation voltage depends on the load and
the V DD1 slew rate.
With a fast V DD1 slew rate (200 μs or less), the peak current draws
up to 100 mA/V of V DD1 . The input voltage goes high faster than
the output can turn on; therefore, the peak current is propor-
tional to the maximum input voltage.
With a slow V DD1 slew rate (in the millisecond range), the input
voltage is not changing quickly when V DD1 reaches the UVLO
minimum voltage. The current surge is approximately 300 mA
because V DD1 is nearly constant at the 2.7 V UVLO voltage. The
behavior during startup is similar to when the device load is a
short circuit; these values are consistent with the short-circuit
current shown in Figure 12.
When starting the device for V ISO = 5 V operation, do not limit
the current available to the V DD1 power pin to less than 300 mA.
The ADuM5401W/ADuM5402W/ADuM5403W devices may
not be able to drive the output to the regulation point if a
current-limiting device clamps the V DD1 voltage during startup.
EMI CONSIDERATIONS
The dc-to-dc converter section of the ADuM5401W/ADuM5402W/
ADuM5403W components must, of necessity, operate at a very
high frequency to allow efficient power transfer through the small
transformers. This creates high frequency currents that can
propagate in circuit board ground and power planes, causing
edge and dipole radiation. Grounded enclosures are recom-
mended for applications that use these devices. If grounded
enclosures are not possible, follow good RF design practices in
the layout of the PCB. See the AN-0971 Application Note for
board layout recommendations.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by
the pulses, indicating input logic transitions. In the absence of
logic transitions at the input for more than 1 μs, periodic sets of
refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses for more than approximately 5 μs, the input side
is assumed to be unpowered or nonfunctional, in which case,
the isolator output is forced to a default low state by the watchdog
timer circuit. This situation should occur only during power-up
and power-down operations.
The limitation on the magnetic field immunity of the
ADuM5401W/ADuM5402W/ADuM5403W is set by the
condition in which induced voltage in the receiving coil of the
transformer is sufficiently large to either falsely set or reset the
decoder. The following analysis defines the conditions under
which this can occur.
The pulses at the transformer output have an amplitude of >1.0 V.
The decoder has a sensing threshold of about 0.5 V, thus estab-
lishing a 0.5 V margin in which induced voltages can be tolerated.
The voltage induced across the receiving coil is given by
V = ( ?dβ/dt )∑π r n2 ; n = 1, 2, … , N
where:
β is the magnetic flux density (gauss).
r n is the radius of the n th turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM5401W/
ADuM5402W/ADuM5403W, and an imposed requirement that
Rev. D | Page 20 of 24
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